1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, more particularly to, the semiconductor device in which a plurality of semiconductor chips is stacked in layers on a package board and sealed in a package, and the method for manufacturing the same.
The present application claims priority of Japanese Patent Application No. 2002-104570 filed on Apr. 5, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
A Large Scale Integration (LSI), which represents semiconductor devices, has been increasingly improved in performance owing to an improvement in integration density, thus finding its applications in a variety of electronic apparatuses. Such semiconductor devices, especially those used in a mobile information processing apparatus such as a cellular phone remarkably proliferated recently, are required to be more compact in order to further give merits of portability thereof while keeping high performance. As the semiconductor device to meet such a requirement is there known such a structure that a plurality of semiconductor chips is stacked in layers on a package board and sealed in a package.
FIG. 20 is a cross-sectional view for showing a structure of one example of a conventional semiconductor device 100 having the above-mentioned structure in which a plurality of semiconductor chips having roughly the same size is stacked one on another. In this semiconductor device 100, as shown in FIG. 20, on a package board 102 having internal terminals 108 and 111 as many as two or more each on its right side of surface and a plurality of projecting external terminals 101 on its back side of surface are there stacked in layers a first semiconductor chip 103 and a second semiconductor chip 104 which have roughly the same size with a spacer chip 105 therebetween and also which are both made of silicon, in such a configuration that pad electrodes 107 on the first semiconductor chip 103 are electrically connected with the internal terminals 108 on the package board 102 by first bonding wires 109, while similarly pad electrodes 110 on the second semiconductor chip 104 are electrically connected with the internal terminals 111 by second bonding wires 112. Furthermore, the first semiconductor chip 103, the spacer chip 105, and the second semiconductor chip 104 are mounted with adhesive agents 113 through 115 respectively. The entire structure including the first and second semiconductor chips 103 and 104 and the first and second bonding wires 109 and 112 on the package board 102 is sealed in a package 106 made of thermo-hardening resin.
As described above, by placing the spacer chip 105 between them, the first and second semiconductor chips 103 and 104 can have a sufficient spacing therebetween. Therefore, the first bonding wires 109 connected to the first semiconductor chip 103 are protected by the spacer chip 105, because the first bonding wires 109 can be prevented from being damaged due to the coming in contact with the second semiconductor chip 104 to short-circuit therewith or vice versa. By providing such a configuration of the semiconductor device 100 in which the respective pluralities of first and second semiconductor chips 103 and 104 are stacked in layers, it is possible to implement such a semiconductor device. The following will describe a method for manufacturing this semiconductor device 100 along steps thereof, with reference to FIGS. 21A to 21F.
First, as shown in FIG. 21A, on the right side of the package board 102 having the respective pluralities of internal terminals 108 and 111 formed on its right side, the first semiconductor chip 103 is mounted via the adhesive agent 113. This first semiconductor chip 103 has the plurality of pad electrodes 107 which is formed at its side edge portions beforehand. Next, as shown in FIG. 21B, the first bonding wires 109 are connected by a wire bonding method between the pad electrodes 107 on the first semiconductor chip 103 and the internal terminals 108 on the package board 102.
Next, as shown in FIG. 21C, the spacer chip 105 made of silicon is mounted on the first semiconductor chip 103 via the adhesive agent 114. As described above, this spacer chip 105 is used to protect the first bonding wires 109. Next, as shown in FIG. 21D, the second semiconductor chip 104 is mounted on the spacer chip 105 via the adhesive agent 115. This second semiconductor chip 104 has the plurality of pad electrodes 110 which is formed at its side edge portions thereon beforehand. Next, as shown in FIG. 21E, the second bonding wires 112 are connected between the pad electrodes 110 on the second semiconductor chip 104 and the internal terminals 111 on the package board 102.
Next, as shown in FIG. 21F, thermo-hardening resin (not shown) is supplied, by a transfer molding method, over the entire structure including the first and second semiconductor chips 103 and 104 and the first and second bonding wires 109 and 112 on the package board 102 and then heated for thermo-hardening, thus completing the package 106.
Subsequently, the plurality of projecting external terminals 101 is formed on the back side of the package board 102, thus completing the semiconductor device 100 as shown in FIG. 20.
It is to be noted that in such a conventional semiconductor device as described above, the spacer chip 105 which is arranged to preserve a sufficient spacing between the first and second semiconductor chips 103 and 104 is made of silicon, which is expensive, so that the device itself is also expensive, which is a disadvantage. Furthermore, as well known, such a semiconductor device as used in a mobile information processing apparatus including a cellular phone is required not only to be more compact but also to be thinner in order to thin a relevant product, which requires in turn that the spacer chip 105 be thinned more. However, although the spacer chip 105 can be polished to a thickness of 20-30 μm owing to an improvement in the polishing technology, such a small thickness may give rise to a trouble in handling after polishing, thus making it difficult to realize a thickness of about 100 μm or less essentially. This gives a restriction on the thinning of the semiconductor devices.
An example of the above-mentioned semiconductor device structure in which a plurality of semiconductor chips is stacked on a package board is disclosed in, for example, Japanese Patent Application Laid-open No. 2001-308262. In a semiconductor device 200 disclosed therein, as shown in FIG. 22, on a package board 202 having a plurality of projecting external terminals 201 formed on its back side, a first semiconductor chip 204 is mounted via an adhesive agent 203, on which is there stacked a second semiconductor chip 205 via an adhesive agent 206, so that the first and second semiconductor chips 204 and 205 are sealed in a package 207 made of resin. Between pad electrodes (not shown) on the first semiconductor chip 204 and internal terminals (not shown) on the package board 202 there are connected first bonding wires 208, while between pad electrodes (not shown) on the second semiconductor chip 205 and internal terminals (not shown) on the package board 202 there are connected second bonding wires 209. Furthermore, the right side of the first semiconductor chip 204 is covered by an overcoat layer 210.
It is to be noted that the adhesive agent 206 used to adhere the first and second semiconductor chips 204 and 205 to each other is intended to be supplied enough to cover the first bonding wires 208 connected to the first semiconductor chip 204 and also to fill a spacing (gap) between the first and second semiconductor chips 204 and 205.
Again, in the semiconductor device disclosed in Japanese Patent Application Laid-open No. 2001-308262, the adhesive agent used to stack the plurality of semiconductor chips is liable to fluctuate in quantity, so that it is difficult to preserve a uniform spacing between the semiconductor chips, thus giving rise to a problem of a decrease in reliability and a difficulty in thinning of the semiconductor device 200.
That is, in the semiconductor device disclosed in the above-mentioned publication in which, as shown in FIG. 22, the first and second semiconductor chips 204 and 205 are stacked one on the other with the adhesive agent 206 therebetween, in which case, however, it is difficult to regulate the quantity of the adhesive agent 206 at a uniform value, which in turn makes it difficult to preserve a uniform spacing between the first and second semiconductor chips 204 and 205. For example, if the adhesive agent 206 is supplied less, the upper-layer second semiconductor chip 205 is liable to be tilted in posture, so that the first bonding wires 208 connected to the first semiconductor chip 204 may come in contact with the second semiconductor chip 205, which is a problem.
Moreover, in this case where the quantity of the supplied adhesive agent 206 is small, a minute gap may readily occur between the first and second semiconductor chips 204 and 205 and be left as it is highly possibly. That is, it is difficult to inject resin into this minute gap in the subsequent process even by the transfer molding method, so that this gap remains as it is. Therefore, the gap, thus left in the semiconductor device 200, is infiltrated by water, to deteriorate the moisture resistance of the semiconductor device 200 as time passes by, thus damaging the reliability thereof.
If, for example, the adhesive agent 206 is supplied in excess, on the other hand, a sufficient spacing is preserved between the first and second semiconductor chips 204 and 205, so that it is possible to prevent the first bonding wires 208 and the second semiconductor chip 205 from coming in contact with each other, but it is difficult to keep the gap therebetween uniform, thus making it difficult to thin the semiconductor device 200. Moreover, in this case where the quantity of the supplied adhesive agent 206 is excessive, an extra quantity of the adhesive agent 206 may flow out of side edge portions of the first semiconductor chip 204 over to the package board 202 to thereby cover the internal terminals (not shown), thus making it difficult to apply the wire bonding method to the second semiconductor chip 205 in the following process. Furthermore, part of the adhesive agent 206, if it flows out of the side edge portions of the semiconductor chip 204, goes through to the first bonding wire 208, so that a difference in coefficient of thermal expansion between this adhesive agent 206 and resin which is used in the following transfer molding process causes stress to be applied on the first bonding wires 208. In the worst case, the first bonding wires 208 may be disconnected finally, thus further deteriorating the reliability of the semiconductor device 200.